Superconductive Logic Circuits With Half Flux Quantum Pulses
Conventional CMOS technology has experienced exponential growth over the past several decades.
The scaling of the transistor has enabled improvement in performance while maintaining low energy dissipation.
However, their scaling is reaching a fundamental physical limitation, encouraging a post CMOS technology to replace it in certain areas and applications.
Single flux quantum (SFQ) logic based on Josephson junctions (JJ) is about five orders of magnitude more energy efficient than CMOS logic while working in tens and hundreds of GHz.
This technology is still far behind CMOS in terms of integration density and complexity.
One major limiting factor in increasing integration density of the technology is the limited scalability of inductors.
In this seminar, two works are presented, the first work introduces a novel device with a data representation of half flux quantum instead of single flux quantum, which leads to a complete inductor-less logic gates.
We design two functionally complete logic gates using this data representation and demonstrate that they can be faster and more energy efficient than conventional rapid single flux quantum (RSFQ) circuits and are more scalable.
In the second work, we present a design methodology for a logic technique that contains the novel JJ, and a mapping algorithm which automatically converts an RSFQ device netlist, to a device netlist containing the novel JJ as presented in the first work and a completely inductor-less logic gates.
Issa is an Ms.C student supervised by Prof. Shahar Kvatinsky.