Transistor design for the reduction of short channel effects in planar and vertical transistors
To overcome the limitations imposed by the low mobility of non-single-crystal materials (organics), our group invented a vertical field-effect structure called “The perforated source vertical transistor.” The advantage of this structure is that short channels (<0.5MUM) are realized without any lithography step. However, while these transistors work, they exhibit parasitic short-channel effects. Specifically, it is practically impossible to realize current saturation in the output characteristics. Hence, my challenge was to alter the transistor design to enter saturation without any loss of maximum current.
We chose two primary materials as semiconductors: solution-processed (sol-gel) InGaZnO and vacuum deposited C60 molecule. The presentation summarizes the work on understanding the downfalls of the vertical architecture and using it to improve the device performance by suggesting new architecture designs. We have combined computer-aided design 2D simulation with device fabrication to study the device performance changes. First, we have focused our attention on the absence of saturation in vertical architecture and the ways to improve them. Second, we addressed the short channel effect arising from the shortening of the device dimensions. Finally, we demonstrate a simple “double injection work function” electrode that mitigates the short-channel effects (realized for 200nm channel length of IGZO TFT). The new device electrode can improve short-channel vertical and planar transistors, making it interesting for future device implementation.
* PhD student under the supervision of Prof. Nir Tessler.