Analog-to-Digital Converter for High-Speed CMOS Image Sensors

Modern electronic systems store and process information in the digital domain. For these systems to interface with real-world analog signals, conversions between analog and digital signals are required. As a result, one of the keys to the success of these systems has been the advance in analog-to-digital converters (abbreviated A/D or ADCs). Analog-to-digital converters (ADCs) are crucial building blocks in today’s systems.

In this MSc. research, we designed a novel ADC architecture for CMOS image sensors (CIS). The ADC consists of two low-resolution SAR ADC stages pipelined using a residual amplifier. This hybrid architecture so-called pipelined SAR ADC combines the advantages of pipelined and SAR ADCs and can acquire good tradeoffs of power area, resolution, and sampling rate. The performance of the proposed pipelined SAR ADC is compared with state-of-the-art CIS ADCs achieving a sampling rate of 1 MS/s and an ENOB of 11.01 with less than 125uW power consumption, enabling a high-speed and area-efficient column-parallel imaging array. The prototype was implemented in a 65 nm CMOS process.

M.Sc. student under the supervision of Professor Emeritus Yael Nemirovsky & Dr. Claudio Jakobson.