High-Speed DSP/DAC/ADC-Based Wireline Transceivers- Samuel M. Palermo

Registration closes on February 26th, 2026

Language: English

Bio:

Samuel Palermo (S’98-M’07-SM’17) received the B.S. and M.S. degrees in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high-speed optical and electrical I/O architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently the J. W. Runyon Jr. Professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, radiation-hardened electronics, and AI computing hardware. He is currently an associate editor for IEEE Journal of Solid-State Circuits and has previously served in this role for IEEE Solid-State Circuits Letters and IEEE Transactions on Circuits and System – II. He has also previously served as a distinguished lecturer for the IEEE Solid-State Circuits Society and on the IEEE CASS Board of Governors.

Course Content

Syllabus:

This course covers system and circuit design techniques of high-speed SERDES transceivers based on DSP, DAC, and ADC blocks. Topics include wireline channels, communication techniques, transmitters, receivers, high-speed digital-to-analog and analog-to-digital converters, equalizers, and clocking circuitry. This course is intended for Analog/Mixed-Signal IC designers and graduate students interested in learning design techniques for state-of-the-art SERDES transceivers used in datacenters, AI systems and communication systems.

Learning Outcomes:

Upon successful completion of the course, the student will be able to:

1. Understand high-speed wireline channel properties and communications techniques
2. Understand link system design utilizing statistical bit-error-rate analysis and modeling tools.
3. Understand the design specifications and implementation details of high-speed SERDES circuits such as drivers, receivers, equalizers, and clocking systems
4. Understand the design specifications and implementation details of high-speed digital-to-analog and analog-to-digital converters

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