Scaling Code and Data in CGRAs

Coarse-grained reconfigurable architectures (CGRAs) have gained significant traction in various fields like high-performance computing (HPC) and machine learning. However, a key challenge lies in the configuration time overhead associated with CGRAs. This remains a fundamental constraint, leading to underutilization, especially noticeable in scenarios requiring frequent reconfigurations or involving large grids.
This research explores two mechanisms to alleviate these limitations. It focuses on improving loop acceleration efficiency by facilitating the passage of loop-carried dependent values across threads within the CGRA fabric and mapping backward edges to inter-thread communication. Additionally, this study explores scale-out CGRA configurations aimed at enhancing the performance of Matrix multiplication, a crucial operation in various domains like machine learning and scientific computing. It optimizes connections between CGRA cores and chiplets, and enables the parallel execution of matrix multiplication tasks. This approach, combined with high-bandwidth connections and support for vector operations, offers a modular and efficient solution for tackling the computational complexity of matrix multiplication.

Ph.D. Under the supervision of Prof. Yoav Etsion.